Arrakis — CMOS inverter

ARRAKISCOMPUTE

CMOS INVERTERTRANSISTOR CROSS-SECTION

INPUT A0

NOT

OUTPUT Y1

Charging output capacitance

A · inputY · outputTime →

Idealized planar CMOS. Carrier motion and time magnified; leakage and quantum effects omitted.

Field, charge, logic.

A CMOS inverter connects the output to VDD through PMOS when A is low, and to ground through NMOS when A is high. The insulated gate changes channel carrier density. Carriers never pass through the gate oxide.

Amber filled particles represent electrons in NMOS. Pale blue open particles represent holes in PMOS. Their drift direction follows charge transport; NMOS electron flow is opposite conventional current.

Output model

C · dY/dt = Gp · (VDD − Y) − Gn · Y

The educational model uses normalized VDD = 1, capacitance C = 1, and active conductance G = 2.8. Ideal switches represent channel turn-on; it does not solve device electrostatics or a measured GPU process. The analog output charges or discharges continuously. Directional particle motion fades as current approaches zero.

Geometry, carrier density and time are illustrative, not to scale. Threshold transitions, short-circuit current, leakage, tunneling and other quantum effects are omitted. These are planar teaching devices, not a literal modern GPU cross-section.

Sources

MIT · MOSFETs and CMOS logic University of Maryland · CMOS inverter MIT · CMOS inverter dynamics